In current power device technology, including Junction Field Effect Transistor (JFET), Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and trench Insulated Gate Bipolar Transistor (IGBT), the use of highly doped poly silicon as a gate material has the advantage of being compatible to conventional silicon processes, but the resulting gate resistance is undesirable since it typically will affect the high frequency performance of the resulting device. In high speed Integrated Circuits (ICs), the use of metal films as gate materials, including molybdenum (Mo), tungsten (W), and silicides, provide lower resistivity, but the process may not be compatible with certain processes in power devices and on some materials such as silicon-carbide (SiC). One or more embodiments address these and other disadvantages in a cost effective manner.